1. Field of the Invention
The present invention relates to a voltage controlled oscillator, and more particularly, to a voltage controlled oscillator which can suppress the deviation of an oscillation frequency.
2. Description of the Related Art
A typical voltage controlled oscillator (VCO) generates an output signal oscillating at a frequency determined in accordance with a voltage supplied from an external unit. For example, the voltage controlled oscillator (VCO) is used in various fields such as information processing and communication.
A conventional voltage controlled oscillator (VCO) will be described with reference to FIG. 1. FIG. 1 is a circuit diagram showing the circuit structure of the conventional voltage controlled oscillator (VCO). Referring to FIG. 1, the conventional voltage controlled oscillator (VCO) 105 is comprised of a bias generator (BG) 108, a ring oscillator (RO) 109, and a level converter (L-C) 107.
A constant voltage Vcnl with a predetermined voltage value and a control voltage Vcnt are supplied from an external unit to the bias generator (BG) 108. Also, a power supply voltage is supplied to the bias generator (BG) 108 and the ring oscillator (RO) 109 from an external unit. The outputs of the bias generator (BG) 108 are supplied to the ring oscillator (RO) 109. The bias generator (BG) 108 compensates for the operation current of the ring oscillator (RO) 109. The compensation means to flow the current enough to rapid rising and falling operations of the ring oscillator (RO) 109. Through this compensation, a high frequency characteristic can be improved. The level converter (L-C) 107 generates an output signal FVCO based on the outputs of the ring oscillator (RO) 109.
The ring oscillator (RO) 109 is comprised of N inversion-type differential amplifier. Here, N is an integer equal to or more than 2. Each of the N inversion-type differential amplifiers operates based on the outputs of the bias generator (BG) 108. That is, the operation current of each of the N inversion-type differential amplifiers is indirectly determined by the addition of a current Icnl determined in accordance with the constant voltage Vcnl and a current Icnt determined in accordance with the control voltage Vcnt. In this way, in the ring oscillator (RO) 109, an offset of the oscillation frequency is set based on the constant voltage Vcnl, and the oscillation frequency is proportional to the voltage Vcnt. The ring oscillator (RO) 109 supplies one of the maximum voltage VOUT1 showing the maximum peak and the minimum voltage VOUT2 showing the minimum peak to the level converter (L-C) 107 through a first output terminal OUT1. Also, the ring oscillator (RO) 109 supplies the other of the maximum voltage VOUT1 and the minimum voltage VOUT2 to the level converter (L-C) 107 through a second output terminal OUT2.
The level converter (L-C) 107 increases voltage difference between the minimum voltage VOUT2 and the maximum voltage VOUT1 to a CMOS level and generates the output signal FVCO. The output signal FVCO generated by the level converter (L-C) 107 is sent out outside as the output signal of the voltage controlled oscillator (VCO) 105.
A relation of the oscillation frequency of the output signal FVCO generated by the voltage controlled oscillator (VCO) 105 and the control voltage Vcnt will be described. FIG. 3 is a diagram showing the relation. Referring to FIG. 3, when the voltage Vcnt increases more than a threshold voltage Va101 of a transistor contained in the voltage controlled oscillator (VCO) 105, the oscillation frequency of the output signal FVCO starts to increase linearly from 0 (Hz), as shown by the symbol X1. Thus, the voltage controlled oscillator (VCO) 105 generates the output signal FVCO with the oscillation frequency proportional to the control voltage Vcnt in a range from the threshold voltage Va101 to the power supply voltage VDD. Therefore, when the control voltage Vcnt is Vb101 (Va101 less than Vb101 less than VDD), the output signal FVCO of a desired oscillation frequency Fb101 can be obtained.
However, the voltage Vb101 receives interference due to a noise component and changes. At that time, the change of the desired oscillation frequency Fb101 becomes large in accordance with the inclination of the frequency characteristic, because the inclination of the frequency characteristic shown by the symbol X1 is steep. To suppress the large change of the oscillation frequency, an offset frequency Fa101 is presented by the addition of the current Icnt corresponding to the constant voltage Vcnt in the bias generator (BG) 108. The offset frequency Fa101 is larger than 0 (Hz) and is smaller than the desired frequency Fb101, and is referred to as a reference frequency or a free-running oscillation frequency. Thus, the voltage controlled oscillator (VCO) 105 can generate the output signal FVCO to have frequency characteristic shown by the symbol Y101 which is more gentle than the frequency characteristic shown by the symbol X1.
Next, the bias generator (BG) 108 will be described. The bias generator (BG) 108 is comprised of an addition circuit 108a and a mirror circuit 108b. 
The addition circuit 108a is comprised of a P-channel MOS (PMOS) transistor 111, and N-channel MOS (NMOS) transistors 112 and 113. The higher side power supply voltage VDD is connected with the source electrode of the PMOS transistor 111. The drain electrode of the PMOS transistor 111 is connected with the drain electrodes of the NMOS transistors 112 and 113. The constant voltage Vcnl is supplied to the gate electrode of the NMOS transistor 112 from the external unit. Also, the source electrode of the NMOS transistor 112 is connected with the lower power supply voltage, and generally is grounded. The voltage Vcnt is supplied to the gate electrode of the NMOS transistor 113 from the external unit. Also, the source electrode of the NMOS transistor 113 is connected with the lower power supply voltage, and generally is grounded.
The mirror circuit 108b is comprised of a PMOS transistor 114 and an NMOS transistor 115. The higher power supply voltage VDD is connected with the source electrode of the PMOS transistor 114. The gate electrode of the PMOS transistor 114 is connected with the drain electrode of the PMOS transistor 111. The drain electrode of the NMOS transistor 115 is connected with the drain electrode of the PMOS transistor 114. Also, the source electrode of the NMOS transistor 115 is connected with the lower power supply voltage, and generally is grounded.
The mirror circuit flows through a second transistor connected with a first transistor, the current with the same value as the value of current which flows through the first transistor or a value proportional to the value of current which flows through the first transistor like a mirror. The current which flows through the second transistor increases proportionally, if the current which flows through the first transistor increases. Therefore, the output of the PMOS transistor 111 is supplied from the bias generator (BG) 108 to the ring oscillator (RO) 109 as a signal corresponding to an addition of the current Icnl determined in accordance with the constant voltage Vcnl and the current Icnt determined in accordance with the voltage Vcnt. Also, the output of the PMOS transistor 114 is supplied from the bias generator (BG) 108 to the ring oscillator (RO) 109.
Next, the ring oscillator (RO) 109 will be described. In the conventional voltage controlled oscillator shown in FIG. 1, the above-mentioned N is an even number equal to or more than 2, and specifically N is 4. In this case, the ring oscillator (RO) 109 is comprised of first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d. Each of the first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d is comprised of PMOS transistors 121, 122, 123, and 124, and NMOS transistor 125, 126, and 129. The first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d have basically the same circuit structure. Therefore, the circuit structure of the first inversion-type differential amplifier 109a will be described.
The higher side power supply voltage VDD is connected with the source electrodes of the PMOS transistors 121, 122, 123, and 124. The gate electrodes of the PMOS transistors 122 and 123 are connected with the drain electrode and gate electrode of the PMOS transistor 111, respectively. Here, each of the PMOS transistors 122 and 123 constitutes a current mirror circuit with the PMOS transistor 111. The gate electrode of the NMOS transistor 129 is connected with the drain electrode and gate electrode of the NMOS transistor 115. Also, the source electrode of the NMOS transistor 129 is connected with the lower power supply voltage, and generally is grounded. Here, the NMOS transistor 129 constitutes a current mirror circuit with the NMOS transistor 115. The drain electrode of the NMOS transistor 129 is connected with the source electrodes of the NMOS transistors 125 and 126. The drain electrode of the NMOS transistor 125 is connected with the drain electrodes of the PMOS transistors 121 and 122, and the gate electrode of the PMOS transistor 121. The drain electrode of the NMOS transistor 126 is connected with the drain electrodes of the PMOS transistors 123 and 124, and the gate electrode of the PMOS transistor 124.
The gate electrode of the NMOS transistor 125 of the second inversion-type differential amplifier 109b is connected with the drain electrode of the NMOS transistor 125 of the first inversion-type differential amplifier 109a. The gate electrode of the NMOS transistor 126 of the second inversion-type differential amplifier 109b is connected with the drain electrode of the NMOS transistor 126 of the first inversion-type differential amplifier 109a. 
Similarly, the gate electrode of the NMOS transistor 125 of the third inversion-type differential amplifier 109c is connected with the drain electrode of the NMOS transistor 125 of the second inversion-type differential amplifier 109b. The gate electrode of the NMOS transistor 126 of the third inversion-type differential amplifier 109c is connected with the drain electrode of the NMOS transistor 126 of the second inversion-type differential amplifier 109b. Also, the gate electrode of the NMOS transistor 125 of the fourth inversion-type differential amplifier 109d is connected with the drain electrode of the NMOS transistor 125 of the third inversion-type differential amplifier 109c. The gate electrode of the NMOS transistor 126 of the fourth inversion-type differential amplifier 109d is connected with the drain electrode of the NMOS transistor 126 of the third inversion-type differential amplifier 109c. Also, the gate electrode of the NMOS transistor 125 of the first inversion-type differential amplifier 109a is connected with the drain electrode of the NMOS transistor 126 of the fourth inversion-type differential amplifier 109d. The gate electrode of the NMOS transistor 126 of the first inversion-type differential amplifier 109a is connected with the drain electrode of the NMOS transistor 125 of the fourth inversion-type differential amplifier 109d. Also, the drain electrode of the NMOS transistor 125 of the fourth inversion-type differential amplifier 109d is connected with the level converter (L-C) 107 through the first output terminal OUT1. The drain electrode of the NMOS transistor 126 of the fourth inversion-type differential amplifier 109d is connected with the level converter (L-C) 107 through the second output terminal OUT2.
Next, the operation of the bias generator (BG) 108 and the ring oscillator (RO) 109 of the above-mentioned voltage controlled oscillator (VCO) 105 will be described with reference to FIG. 1. Here, a reference level is biased to the constant voltage Vcnl and a control level is biased to the voltage Vcnt, which are supplied to the voltage controlled oscillator (VCO) 105.
Referring to FIG. 1, the NMOS transistor 112 flows the drain current ID112 in accordance with the constant voltage Vcnl as a bias. However, it is supposed that the drain current ID113 of the NMOS transistor 113 is 0 (A), because the NMOS transistor 113 is now in the off state, or the control voltage Vcnt does not reach the threshold voltage. Because the gate and drain of the PMOS transistor 111 are connected to a same node, the PMOS transistor 111 is in the saturation region. At this time, the gate voltage level of the PMOS transistor 111 is equal to the gate levels of the PMOS transistor 114 of the mirror circuit 108b, and each of the PMOS transistor 122 and 123 in each of the first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d in the ring oscillator (RO) 109. Each of the PMOS transistor 114 and the PMOS transistor 122 and 123 in each of the first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d constitutes a current mirror circuit with the PMOS transistor 111. Therefore, the current determined in accordance with the ratio of the gate parameters of the PMOS transistor 111 such as the threshold voltage, the gate length, and the gate thickness of the gate oxidation film and those of each of the PMOS transistors 114, 122 and 123 flows as the drain current of each of the PMOS transistors 114, 122 and 123.
As the drain current ID115 of the NMOS transistor 115, only the drain current ID114 of the PMOS transistor 114 flows which is determined in accordance with the ratio of the gate parameters of the PMOS transistor 111 and those of the PMOS transistor 114. Because the gate and drain of the NMOS transistor 115 are connected to the same node, the NMOS transistor 115 is in the saturation region, and the gate voltage level is determined to flow the drain current ID115. The gate voltage level is equal to the gate level of the NMOS transistor 129 of each of the first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d. The NMOS transistors 129 of each of the first to fourth inversion-type differential amplifiers 109a, 109b, 109c, and 109d constitutes a current mirror circuit with the NMOS transistor 115. Therefore, the current determined in accordance with the ratio of the gate parameters of the NMOS transistor 115 and those of the NMOS transistor 129 flows as the drain current of the NMOS transistor 129.
When the control voltage Vcnt rises and becomes equal to or higher than the threshold value of the NMOS transistor 113, the NMOS transistor 113 is turned on. At this time, the drain current ID113 of the NMOS transistor 113 begins to flow. As the voltage Vcnt raises, the drain currents ID113 of the NMOS transistor 113 flows more. Therefore, the drain current ID111 of the PMOS transistor 111 increases, too. Consequently, the drain current of each of the PMOS transistors 122 and 123 of the current mirror circuits, and the drain current of the NMOS transistor 129 increase, too.
When the reference level is biased to the constant voltage Vcnl and the voltage Vcnt is not supplied, the drain current ID129 flows through the NMOS transistor 129 of the first inversion-type differential amplifier 109a. Thus, the drain current ID129 of the NMOS transistor 129 flows through a node where the source electrodes of the NMOS transistors 125 and 126 are connected with the drain electrode of the NMOS transistor 129 in common.
The NMOS transistors 125 and 126 of the differential circuit as a switch operate with the drain current ID129 of the above-mentioned NMOS transistor 129. The NMOS transistors 125 and 126 in the first inversion-type differential amplifier 109a flow the drain currents ID125 and ID126 in accordance with input signals, i.e., output signals from the fourth inversion-type differential amplifier 109d to supply to the PMOS transistors 121 and 124 as active loads. When the NMOS transistor 125 is turned on and the NMOS transistor 126 is turned off, the current flows through the NMOS transistor 125 and the PMOS transistor 121. At this time, the output of the NMOS transistor 125 in the first inversion-type differential amplifier 109a or the input of the NMOS transistor 125 in the second inversion-type differential amplifier 109b becomes low because of the potential drop corresponding to the drainxe2x80x94source voltage VDS121 of the PMOS transistor 121. Because the NMOS transistor 126 is in the off state, the output of the NMOS transistor 126 in the first inversion-type differential amplifier 109a or the input of the NMOS transistor 126 of the second inversion-type differential amplifier 109b becomes high.
The PMOS transistors 122 and 123 connected in parallel as the active loads constitute mirror circuits together with the bias generator (BG) 108. By flowing the mirror current through the mirror circuit, there is an effect that the NMOS transistors 125 and 126 flow currents quickly when the NMOS transistors 125 and 126 are turned on or off. Thus, it is possible to make the rising and falling operations rapid to promote the oscillation at high speed.
When the level of the voltage Vcnt supplied to the bias generator (BG) 108 rises, the drain current ID129 of the NMOS transistor 129 of first inversion-type differential amplifier 109 begins to flow. At this time, the circuit current of the first inversion-type differential amplifier 109a increases. If the current increases, the drive ability for the circuit increases. Also, the time taken to charge output load, i.e., the gate capacitances of the NMOS transistor 125 and the NMOS transistor 126 of the second inversion-type differential amplifier 109b and wiring lines capacities can be made short. In other words, a delay time in the first inversion-type differential amplifiers 109a becomes short.
When the NMOS transistor 125 of the first inversion-type differential amplifier 109a is turned on and the NMOS transistor 126 is in the off state, as mentioned above, the output of the NMOS transistor 125 is in the low level and the output of the NMOS transistor 126 is in the high level. Thus, the low level is supplied from the NMOS transistor 125 of the first inversion-type differential amplifier 109a to the NMOS transistor 125 of the second inversion-type differential amplifier 109b. Also, the high level is supplied from the NMOS transistor 126 of the first inversion-type differential amplifier 109a to the NMOS transistor 126 of the second inversion-type differential amplifier 109b. Therefore, the NMOS transistor 125 is turned off and the NMOS transistor 126 is turned on in the second inversion-type differential amplifier 109b. As a result, the output of the NMOS transistor 125 is in the high level and the output of the NMOS transistor 126 is in the low level. Thus, the high level is supplied from the NMOS transistor 125 of the second inversion-type differential amplifier 109b to the NMOS transistor 125 of the third inversion-type differential amplifier 109c. Also, the low level is supplied from the NMOS transistor 126 of the second inversion-type differential amplifier 109b to the NMOS transistor 126 of the third inversion-type differential amplifier 109c. Therefore, the NMOS transistor 125 is turned on and the NMOS transistor 126 is turned off in the third inversion-type differential amplifier 109c. As a result, the output of the NMOS transistor 125 is in the low level and the output of the NMOS transistor 126 is in the high level. Thus, the low level is supplied from the NMOS transistor 125 of the third inversion-type differential amplifier 109c to the NMOS transistor 125 of the fourth inversion-type differential amplifier 109d. Also, the high level is supplied from the NMOS transistor 126 of the third inversion-type differential amplifier 109c to the NMOS transistor 126 of the second inversion-type differential amplifier 109d. Therefore, the NMOS transistor 125 is turned off and the NMOS transistor 126 is turned on in the second inversion-type differential amplifier 109b. As a result, the output of the NMOS transistor 125 is in the high level and the output of the NMOS transistor 126 is in the low level. The high level is supplied from the NMOS transistor 125 of the fourth inversion-type differential amplifier 109d to the NMOS transistor 126 of the first inversion-type differential amplifier 109a. Also, the low level is supplied from the NMOS transistor 126 of the fourth inversion-type differential amplifier 109d to the NMOS transistor 125 of the first inversion-type differential amplifier 109a. By this, the NMOS transistor 125 is turned off and the NMOS transistor 126 is turned on in the first inversion-type differential amplifier 109a. Thus, the high level is supplied from the NMOS transistor 125 of the first inversion-type differential amplifier 109a to the NMOS transistor 125 of the second inversion-type differential amplifier 109b. Also, the low level is supplied from the NMOS transistor 126 of the first inversion-type differential amplifier 109a to the NMOS transistor 126 of the second inversion-type differential amplifier 109b. Therefore, the NMOS transistor 125 is turned on and the NMOS transistor 126 is turned off in the second inversion-type differential amplifier 109b. 
As described above, first, the NMOS transistor 125 is in the on state and the NMOS transistor 126 is in the off state in the first inversion-type differential amplifier 109a. However, when a process proceeds for one circulation from the first inversion-type differential amplifier 109a to the fourth inversion-type differential amplifier 109d, the NMOS transistor 125 is turned off and the NMOS transistor 126 is turned on in the first inversion-type differential amplifier 109a. Because this operation continues, the oscillation is carried out.
In the conventional voltage controlled oscillator (VCO) 105, the inclination of the frequency characteristic can be made gentle, because the offset is given to the above-mentioned free-running oscillation frequency Fa101. Therefore, even when the control voltage Vcnt containing a noise component is supplied, the change of the above-mentioned oscillation frequency Fb101 can be made small, compared with the voltage controlled oscillator in which the offset is not given.
The frequency characteristic of the conventional voltage controlled oscillator (VCO) 105 will be described with reference to FIG. 4. FIG. 4 is a diagram showing the frequency characteristic of the conventional voltage controlled oscillator (VCO).
As shown in FIG. 4, the symbol Y101 shows a frequency characteristic in case of xe2x80x9ctyp-casexe2x80x9d. The free-running oscillation frequency Fa101 in this case is about 500 MHz. The case xe2x80x9ctyp-casexe2x80x9d means a case that there is no manufacture deviation. Such a characteristic is achieved when the threshold voltages Vtn of the NMOS transistors corresponding to Va101, Va102 and Va103 in FIG. 14 and the threshold voltages Vtp of the PMOS transistors have center values of normal distributions. However, when the deviation during manufacture exists, there are the frequency characteristic in case of xe2x80x9cfast-casexe2x80x9d shown by the symbol Y101xe2x80x2 and the frequency characteristic in case of xe2x80x9cslow-casexe2x80x9d shown by the symbol Y101xe2x80x3. The frequency characteristic in the case of xe2x80x9cfast-casexe2x80x9d is obtained when the threshold voltages Vtn and Vtp are lower. At this time, a transistor is turned on earlier, a parasitic capacity becomes few and a signal is sent earlier. The frequency characteristic in the case of xe2x80x9cslow-casexe2x80x9d is obtained when the threshold voltages Vtn and Vtp are higher. At this time, the transistor is turned on late, the parasitic capacity is more, and the signal is sent late. Also, sometimes there are the deviations of the threshold voltages Vtn and Vtp.
When a frequency characteristic is determined considering deviation during the manufacture, the upper limit is shown as MAX of the symbol Y101xe2x80x2 and the lower limit is shown as MIN of the symbol Y101xe2x80x3. Here, it is supposed that the voltage for the output signal FVCO of the desired oscillation frequency Fb101 is Vb101 (Va101 less than Vb101 less than VDD), and the oscillation frequency Fb101 is 1000 MHz. In this condition, in the frequency characteristic in case of xe2x80x9cfast-casexe2x80x9d shown by the symbol Y101xe2x80x2, the free-running oscillation frequency Fa102 is about 600 MHz. This is faster by about 20%, compared with the frequency characteristic in case of xe2x80x9ctyp-casexe2x80x9d shown by the symbol Y101. However, when the voltage Vcnt increases and reaches the voltage Vb101 in case of the xe2x80x9ctyp-casexe2x80x9d shown by the symbol Y101, it becomes about 1000 MHz. However, in the frequency characteristic in case of xe2x80x9cfast-casexe2x80x9d shown by the symbol Y101xe2x80x2, it has become as much as 1550 MHz which is faster by 55% than the case of xe2x80x9ctyp-casexe2x80x9d. In the frequency characteristic in case of xe2x80x9cslow-casexe2x80x9d shown by the symbol Y101xe2x80x3, the free-running oscillation frequency Fa103 is about 400 MHz. This is later by about 20%, compared with the frequency characteristic in the case of xe2x80x9ctyp-casexe2x80x9d shown by the symbol Y101. However, in the frequency characteristic in the case of xe2x80x9ctyp-casexe2x80x9d shown by the symbol Y101, it becomes about 1000 (MHz) when the voltage Vcnt becomes large and becomes the level of Vb101. However, in the frequency characteristic of xe2x80x9cslow-casexe2x80x9d shown by the symbol Y101xe2x80x3, it becomes as much as 600 MHz which is later by 40% than the case of xe2x80x9ctyp-casexe2x80x9d.
In this way, in the conventional voltage controlled oscillator (VCO) 105, the deviation of the frequency characteristic falls within 20% in case of the free-running oscillation. However, when the control voltage Vcnt increases, the deviation becomes large to 55% on the side of the upper limit (the frequency characteristic shown by the symbol Y101xe2x80x2) and large to 40% on the side of the lower limit (the frequency characteristic shown by the symbol Y101xe2x80x3). This is because many current mirror circuits are used in the voltage controlled oscillator (VCO) 105. The deviation of the oscillation frequency becomes large due to the channel length modulation effect. In the recent LSI, the channel length modulation effect becomes more conspicuous, because the size of the transistor becomes small.
The channel length modulation effect is an effect that the drain current becomes large in accordance with the increase of the drain voltage in the saturation region. This effect changes the drain current in accordance with the change of the drain voltage, resulting in the change of the oscillation frequency.
Nest, the structure of a PLL (phase-Locked loop) circuit using the conventional voltage controlled oscillator (VCO) 105 will be described with reference to FIG. 2. FIG. 2 is a block diagram showing the structure of the PLL circuit using the conventional voltage controlled oscillator (VCO).
As shown in FIG. 2, the PLL circuit is comprised of a phase frequency comparator (PFD) 101, a charge pump 102, a loop filter 103, an offset circuit (OFST) 104, the voltage controlled oscillator (VCO) 105 and a frequency divider 106.
The phase frequency comparator (PFD) 101 compares the input signal Fref and the feedback signal Ffb from the frequency divider 106 in phase and frequency, and generates an increment signal UP and a decrement signal DOWN to show an error between these signals. For example, it is supposed that a clock signal front an oscillator (not shown) is used as the input signal Fref. The increment signal UP generated by the phase frequency comparator (PFD) 101 has a frequency decrease quantity of the feedback signal Ffb to the input signal Fref and a pulse width equivalent to phase delay. Also, the decrement signal DOWN has a frequency increase quantity of the feedback signal Ffb to the input signal Fref and a pulse width equivalent to the phase progress. The increment signal UP and the decrement signal DOWN generated by the phase frequency comparator (PFD) 101 are supplied to the charge pump 102.
The charge pump 102 is a charge pump with a single output, and generates a current pulse in accordance with each of the pulse widths of the increment signal UP and the decrement signal DOWN and supplies to the loop filter 103. In response to the current pulse supplied from the charge pump 102, the loop filter 103 charges a capacitor (not shown) and discharges the charge from the capacitor (not shown) and generates the voltage Vcnt in accordance with the above-mentioned current pulse. The voltage Vcnt generated by this the loop filter 103 is supplied to the voltage controlled oscillator (VCO) 105.
The offset circuit (OFST) 104 generates and supplies the constant voltage Vcnl to the bias generator (BG) 108 of the voltage controlled oscillator (VCO) 105. The constant voltage Vcnl is supplied from the offset circuit (OFST) 104 to the bias generator (BG) 108 of the voltage controlled oscillator (VCO) 105, and the voltage Vcnt is supplied from the loop filter 103. The voltage controlled oscillator (VCO) 105 generates the output signal FVCO to oscillate at a frequency determined in accordance with the constant voltage Vcnl supplied from the offset circuit (OFST) 104 and the voltage Vcnt supplied from the loop filter 103. This oscillation frequency is indirectly determined based on the addition of the current Icnl determined in accordance with the constant voltage Vcnl and the current Icnt determined in accordance with the voltage Vcnt. In the lock state, the voltage controlled oscillator (VCO) 105 oscillates at the frequency of M (M is a real number) times of the frequency of the input signal Fref.
The output signal FVCO generated by the voltage controlled oscillator (VCO) 105 is sent out outside as the output signal of the PLL circuit and is supplied to the frequency divider 106. The frequency divider 106 divides in frequency the output signal FVCO to 1/N and supplies to the phase frequency comparator (PFD) 101.
Next, the operation of the PLL circuit using the conventional voltage controlled oscillator (VCO) 105 will be described.
It is supposed that the phase of the feedback signal Ffb fed back from the frequency divider 106 to the phase frequency comparator (PFD) 101 is now late from the phase of the input signal Fref. In this case, the phase frequency comparator (PFD) 101 generates the increment signal UP which has a frequency decrease quantity and a pulse width equivalent to the phase delay and supplies to the charge pump 102. The charge pump 102 flows current determined in accordance with increment signal UP to charge the capacitor (not shown) in the loop filter 103. By this, the voltage Vcnt generated by the loop filter 103 becomes high. As a result, the oscillation frequency of the output signal FVCO outputted from the voltage controlled oscillator (VCO) 105 rises and the phase of the output signal FVCO progresses and approaches the phase of the input signal Fref.
On the other hand, when the phase of the feedback signal Ffb is progressive from the phase of the input signal Fref, the phase frequency comparator (PFD) 101 generates the decrement signal DOWN which has a frequency increase quantity and a pulse width equivalent to the phase progress and supplies to the charge pump 102. The charge pump 102 discharges the charge from the capacitor (not shown) in the loop filter 103 by dragging current determined in accordance with the decrement signal DOWN. By this, the voltage Vcnt outputted from the loop filter 103 becomes low. As a result, the oscillation frequency of the output signal FVCO outputted from the voltage controlled oscillator (VCO) 105 decreases and the phase of the output signal FVCO is delayed and approaches the phase of the input signal Fref.
In this way, in the PLL circuit using the conventional voltage controlled oscillator (VCO) 105, the output signal FVCO and the input signal Fref are always compared in frequency and phase, and the feedback control is carried out to correct the phase delay or phase progress of the output signal FVCO if the phase delay or phase progress between the output signal FVCO and the input signal Fref exists. Then, if the phase delay or phase progress falls within a predetermined range, the phase frequency comparator (PFD) 101 generates the increment signal UP and the decrement signal DOWN which have an identical short pulse width. The quantity of the charge charged in and discharged from the capacitor (not shown) in the loop filter 103 becomes equal to balance, and the PLL circuit enters the lock state. In this lock state, the phase of the output signal FVCO is coincident with the phase of the input signal Fref. However, in the PLL circuit using the conventional voltage controlled oscillator (VCO) 105, when a noise component is contained in the voltage Vcnt outputted from the loop filter 3, because an offset frequency is given the PLL circuit, the change of the desired oscillation frequency can be suppressed small, compared with the PLL circuit in which the offset frequency is not given. However, because many current mirror circuits are used, the deviation of the oscillation frequency due to the deviation in the manufacture cannot be suppressed low.
A frequency synthesizer circuit as another PLL circuit using another conventional voltage controlled oscillator (VCO) is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 8-125531), in which the phase change of an RF modulation signal due to external disturbance can be prevented for good modulation precision. The frequency synthesizer circuit is comprised of an offset signal generating circuit which generates an offset voltage to cancel the frequency change due to an external disturbance signal based on a disturbance signal as a cause to change the frequency of a local oscillation signal outputted from a voltage controlled oscillator. An offset signal adding circuit adds the offset voltage from the offset signal generating circuit to a tuning voltage to supply to the voltage controlled oscillator.
Also, another PLL circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-177416), in which an oscillation frequency is not influenced and the step out of a lock state can be prevented, irrespective of the deviation of the manufacture state, even if a voltage signal changes due to power supply voltage change and temperature change so that control characteristic is changed. This PLL (the phase-locked loop) circuit is comprised of a phase-locked loop circuit section which generates a DC voltage signal from an error signal as the result of phase comparison between an oscillation signal and a reference signal. A voltage controlled oscillation circuit outputs the oscillation signal controlled in frequency in response to the voltage signal level. A manufacture condition detecting section examines device characteristic change caused due to the change of the manufacture condition, and outputs a corresponding process change signal. A voltage offset section sets an offset value such that a center value of the voltage signal is in neighborhood of a level at the time of the frequency lock in response to the supply of the process change signal.
Also, a phase frequency comparator is described in detail in xe2x80x9cA 622-MHz CMOS phase-Locked Loop with Precharge-Type Phase Frequency Detectorxe2x80x9d (Symposium on VLSI Circuits Digest of Technical Papers, (1994), pp. 129-130) by Hiromi Notani.
Many current mirror circuits are contained in the conventional voltage controlled oscillator (VCO) 105. When a transistor with a small size is used like recently, at change factor due to the channel length modulation effect becomes large. Therefore, in the conventional voltage controlled oscillator (VCO), the deviation of the oscillation frequency becomes large, because the channel length modulation effect is added for the number of stages of the current mirror circuits.
As mentioned above, because the deviation of the oscillation frequency is large, there are the following problems in the conventional voltage controlled oscillator (VCO).
The conventional voltage controlled oscillator (VCO) 105 has a large deviation of the oscillation frequency, because the channel length modulation effect is added to the deviation in the manufacture. Even if the control voltage Vcnt is increased to the power supply voltage VDD in the frequency characteristic shown by the symbol Y101xe2x80x3 in FIG. 4 when a gain is the smallest, there is a fear that the oscillation frequency becomes smaller than the desired frequency Fb101. Therefore, to achieve the desired frequency Fb101 even if there is deviation in the manufacture, the gain of conventional voltage controlled oscillator (VCO) 105 needs to be made large (making the frequency characteristic steep). In this case, when the noise component is on the control voltage Vcnt, the change of the oscillation frequency becomes large.
Also, considering the change of the oscillation frequency changes, it is not possible to widen the range of the oscillation frequency controllable in a range of the control voltage Vcnt. That is, the conventional voltage controlled oscillator (VCO) 105 cannot secure the controllable frequency range. As shown in FIG. 4, the frequency range of the conventional voltage controlled oscillator (VCO) 105 is shown by the symbol F100. This frequency range F100 shows a range from the free-running oscillation frequency Fa102 in the frequency characteristic shown by the symbol Y101xe2x80x2 to the oscillation frequency when the control voltage Vcnt is equal to the power supply voltage VDD in the frequency characteristic shown by the symbol Y101xe2x80x3. The desired oscillation frequency Fb101 is not contained in the frequency range F100.
Therefore, an object of the present invention is to provide a voltage controlled oscillator and a PLL circuit using it, in which the deviation of an oscillation frequency can be suppressed.
Another object of the present invention is to provide a voltage controlled oscillator and a PLL circuit using it, in which jitter can be reduced.
Still another object of the present invention is to provide a voltage controlled oscillator and a PLL circuit using it, which can take a frequency range more widely.
In an aspect of the present invention, a voltage controlled oscillator includes N (N is an integer equal to or more than 2) inversion-type differential amplifiers and a level converter. The N (N is an integer equal to or more than 2) inversion-type differential amplifiers are connected in a loop such that each of output signals outputted from one of the N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of the N inversion-type differential amplifiers. The level converter is connected to one of the N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate an oscillation signal from the output signals outputted from the last inversion-type differential amplifier. Each of the N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage.
Here, operation current of each of the N inversion-type differential amplifiers is determined based on the predetermined voltage and the control voltage. Also, the operation current of each of the N inversion-type differential amplifiers is directly determined based on a summation of a current determined based on the predetermined voltage and a current determined based on the control voltage.
Also, an offset of a frequency of the oscillation signal is set based o the predetermined voltage, and a frequency of the oscillation signal is determined based on the control voltage in a predetermined voltage range. The frequency of the oscillation signal is proportional to the control voltage in the predetermined voltage range.
Also, the voltage controlled oscillator may further include a bias generator which improves current drive ability of the N inversion-type differential amplifiers.
Also, each of the N inversion-type differential amplifiers may include a differential section, a first current source transistor and a second current source transistor. The differential section is connected to a higher power supply voltage and including a pair of differential operation transistors to operate a differential amplifying operation. The first current source transistor is connected between the differential section and a lower power supply voltage and having a gate supplied with a predetermined voltage. The second current source transistor is connected between the differential section and the lower power supply voltage in parallel to the first current source transistor and having a gate supplied with a control voltage.
In this case, the voltage controlled oscillator (may further include a bias generator which controls the differential amplifying operation of each of the N inversion-type differential amplifiers based on the predetermined voltage. In this case, the bias generator may include a first drive transistor and a specific transistor. The first drive transistor is connected to the lower power supply voltage and having a gate electrode supplied with the predetermined voltage. The specific transistor is connected between the higher power supply voltage and the first drive transistor, and having a gate thereof connected with a drain electrode thereof to be driven by the first drive transistor such that the specific transistor controls the differential amplifying operation of each of the N inversion-type differential amplifiers.
Here, the differential section of each of the N inversion-type differential amplifiers may include a pair of first and second load transistors provided for a corresponding one of the differential operation transistors. The first load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to a drain thereof, and the second load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to the drain of the specific transistor. It is desirable that the specific transistor and the second load transistor constitute a current mirror circuit.
Also, the bias generator may further include a second drive transistor connected between the lower power supply voltage and the specific transistor in parallel to the first drive transistor and having a gate electrode supplied with the control voltage. The specific transistor is driven by the second drive transistor in addition to the first drive transistor such that the specific transistor controls the differential amplifying operation of each of the N inversion-type differential amplifiers.
Here, the differential section of each of the N inversion-type differential amplifiers may include a pair of first and second load transistors provided for a corresponding one of the differential operation transistors. In this case, the first load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to a drain thereof, and the second load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to the drain of the specific transistor. It is desirable that the specific transistor and the second load transistor constitute a current mirror circuit.
Also, the differential section of each of the N inversion-type differential amplifiers may include a resistance provided for a corresponding one of the differential operation transistors, and connected between the higher power supply voltage and the corresponding differential operation transistor.
In another aspect of the present invention, a voltage controlled oscillator for generating an oscillation signal, includes an offset section for determining an offset frequency based on a predetermined voltage, and a proportion section for controlling a frequency of the oscillation signal to be proportional to a predetermined voltage. The frequency of the oscillation signal is directly determined based on the predetermined voltage and the control voltage.
In yet another aspect of the present invention, a voltage controlled oscillator for generating an oscillation signal includes an offset means for determining an offset frequency based on a predetermined voltage and a proportion means for controlling a frequency of the oscillation signal to be proportional to a control voltage. The frequency of the oscillation signal is directly determined based on the predetermined voltage and the control voltage. The voltage control oscillator has N inversion-type differential amplifiers, and each of said inversion-type differential amplifiers is directly connected at a single element to either the control voltage or the predetermined voltage.
In still another aspect of the present invention, a phase locked loop (PLL) circuit includes a phase frequency comparator, a control voltage generating section, a voltage controlled oscillator and a frequency divider. The phase frequency comparator compares a reference signal and a feedback signal and generate a difference signal based on the comparison result. The control voltage generating section generates a control voltage in response to the difference signal. The voltage controlled oscillator generates an oscillation signal based on the control voltage and a predetermined voltage. The frequency divider carries out a frequency division to the oscillation signal outputted from the voltage controlled oscillator to produce the feedback signal.
The voltage controlled oscillator may include N (N is an integer equal to or more than 2) inversion-type differential amplifiers and a level converter. The N (N is an integer equal to or more than 2) inversion-type differential amplifiers are connected in a loop such that each of output signals outputted from one of the N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of the N inversion-type differential amplifiers. The level converter connected to one of the N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate the oscillation signal from the output signals outputted from the last inversion-type differential amplifier. Each of the N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage.
Also, operation current of each of the N inversion-type differential amplifiers is directly determined based on a summation of a current determined based on the predetermined voltage and a current determined based on the control voltage.
Also, the PLL circuit may further include a bias generator which improves current drive ability of the N inversion-type differential amplifiers.
Also, each of the N inversion-type differential amplifiers may include a differential section, a first current source transistor, and a second current source transistor. The differential section is connected to a higher power supply voltage and including a pair of differential operation transistors to operate a differential amplifying operation. The first current source transistor is connected between the differential section and a lower power supply voltage and having a gate supplied with a predetermined voltage. The second current source transistor is connected between the differential section and the lower power supply voltage in parallel to the first current source transistor and having a gate supplied with a control voltage. The PLL circuit may further include a bias generator which controls the differential amplifying operation of each of the N inversion-type differential amplifiers based on the predetermined voltage.
In this case, the bias generator may include a first drive transistor and a specific transistor. The first drive transistor is connected to the lower power supply voltage and having a gate electrode supplied with the predetermined voltage. The specific transistor is connected between the higher power supply voltage and the first drive transistor, and having a gate thereof connected with a drain electrode thereof to be driven by the first drive transistor such that the specific transistor controls the differential amplifying operation of each of the N inversion-type differential amplifiers.
In this case, the differential section of each of the N inversion-type differential amplifiers may include a pair of first and second load transistors provided for a corresponding one of the differential operation transistors. The first load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to a drain thereof, and the second load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to the drain of the specific transistor. Also, it is desirable that the specific transistor and the second load transistor constitute a current mirror circuit.
Also, the bias generator may further include a second drive transistor connected between the lower power supply voltage and the specific transistor in parallel to the first drive transistor and having a gate electrode supplied with the control voltage. The specific transistor is driven by the second drive transistor in addition to the first drive transistor such that the specific transistor controls the differential amplifying operation of each of the N inversion-type differential amplifiers.
In this case, the differential section of each of the N inversion-type differential amplifiers may include a pair of first and second load transistors provided for a corresponding one of the differential operation transistors. The first load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to a drain thereof, and the second load transistor is connected between the higher power supply voltage and the corresponding differential operation transistor and has a gate connected to the drain of the specific transistor. It is desirable that the specific transistor and the second load transistor constitute a current mirror circuit.
Also, the differential section of each of the N inversion-type differential amplifiers may include a resistance provided for a corresponding one of the differential operation transistors, and connected between the higher power supply voltage and the corresponding differential operation transistor.